OSIRIS SCHEMATIC MIGRATION
Rapid and efficient schematic migration is an essential tool for evaluating target processes for full chips and IP cores. Migrated circuits using components from a new PDK can then be simulated to evaluate their performance in the new process. This is particularly important for IP companies who need to license analog cores to new customers in unfamiliar processes.
OSIRIS's mapping, placement and re-wiring capabilities take it far beyond the functionality of a simple component swapper. Interactive GUIs find circuit symbols in the source design and guide the mapping of pins and parameters to the target symbol and reference libraries such as standard cells can be replaced with versions from the new foundry.
Physical differences between PDKs such as cell origin, symbol size or pin differences are automatically resolved. Rewiring tools allow new pins to be added and tied to specified nets while stray wires from deleted pins are cleaned from the circuit. Component checking and re-wiring ensures that full circuit hierarchies are migrated in a single pass.
The complexities of property translation between source and target PDKs are handled automatically without users needing to convert between types. Optional recalculation can be invoked to adjust physical parametes to retain passive values.
Pin and Parameter Mapping
The task of mapping pins and parameters between PDKs is controlled through the OSIRIS graphical interfaces. Information from the original and new PDKs are identified and presented to the user in a clear format for easy mapping and conversion. Values can be modified by simple scaling or through complex relationships as required.
Pins are automatically rerouted to ensure connectivity even when symbols and pin positions differ and shorts caused by new pin locations are automatically identified and resolved.
Intelligent parameter assignment and callback triggers allow even the most complex components to be converted for simulation or layout constraints. Advanced commands also deal with complex demands and component modifications to resolve difficult constraints in the target process.
Capabilities and Features
OSIRIS schematic migration features a host of features and capabilities that make it the most powerful and versatile schematic migration tool available. From legacy processes through to the most advanced nanometer and FinFET designs, OSIRIS tools can migrate the most complex designs between processes from independent manufacturers and custom foundries.
Advanced features of the schematic databases such as hierarchical parameters and netset properties are fully retained to deliver a completely migrated schematic which contains the full functionality of the original design.
API level extensions allow the flow to be customized to meet the demands of the most complex migration requirements. From transistor adjustments to complex passive calculations, OSIRIS has been used to solve the most difficult mapping and translation challenges to rapidly move IP to new foundries and processes.
Interactive Schematic Comparison
Checking that the migrated schematic maintains the integrity of the circuit while following the intent of the migration is an essential part of circuit migration. OSIRIS features a dedicated migration comparison tool that check the placement, connectivity and parameters of the target circuit to ensure it matches the original.
Unlike an LVS tool, schematic comparison accounts for differences in component names, parameter types and values to instantly identify discrepancies between old and new circuits. Problems such as max/min size violations or component crowding are reported and highlighted within the schematic editor for easy identification and resolution.
Fast and Hierarchical Migration
OSIRIS migrations can handle a single cell, a defined hierarchy, or an entire design in a single path. You can map the reference library to a flow so that the entire design is udpated to use the symbols and standard cells of the new process.
Scaling and Grid Force
The new PDK has large symbols and different database units that may need to be resolved during the migration process. OSIRIS can add user-defined scale and grid elements during migration to apply new PDK constraints.
Automatic Symbol Offset
OSIRIS automatically recognizes the offset between the source and target symbols and adjusts the symbol's position to align correctly with the circuit wiring. Offsets between primitive components and standard cell libraries are resolved without the need for user calculations. Saves the hassle of entering offset information for potentially hundreds of components.
Automatic Pin Rewiring
Changes in symbol size and pin position between PDKs mean that the symbol pins are not aligned with the wiring. This is detected during the migration process and reconnects the wires if there is a large difference in size between the old and new symbols, or if a pin moves within the symbol.
Rewiring the Short Circuit Location
The added pins of the new component can be short-circuited to the existing wiring, damaging the functionality of the circuit. OSIRIS finds these shorts during the migration process and automatically rewires the wires around them.
Remove Redundant Wiring
The new symbol may have fewer pins than the original PDK, which is a problem with unconnected wires in the new schematic. OSIRIS finds and removes redundant wiring as part of the migration process and warns the schematic of open wires.
OSIRIS allows full flow customization within the Cadence toolset using the Skill ™ programming language. Optional extension routines allow users to fine-tune the migration flow to manage complex circuit elements and adapt to special requirements.
OSIRIS extension routines are automatically called as part of the migration process to allow you to migrate circuit hierarchies in a single pass.
Whether porting IP cores or full chips, IN2FAB's OSIRIS technology allows rapid migration of existing analog and mixed signal IP in a fraction of the time taken for redesign.