Gate simulation / formal verification
SimXACT's innovative analysis technology dynamically performs formal verification in simulation to diagnostically isolate False Xs noise (X-pessimism and glitches), zero-delay race conditions, library modeling errors, and connectivity issues. By automatically resolving the above, high-speed and effective gate-level simulation is possible.
SimXACT provides a utility that allows you to debug and isolate the source of the original X problem that the gate simulation fails.
Eliminate GLS X-pessimism
Enhanced formal logic simulation that dynamically performs repairs in parallel with X-pessimism analysis X propagation in datapath and gate clock logic can be reused in continuous simulation execution without the overhead of analysis tools or licenses False X fix DUT parallel analysis block by block to support large design hierarchy flow Zero race condition with zero delay GLS conflicts can occur with zero delay GLS in designs with gated clocks and delay lines There is sex.
The "pseudo SDF" generator efficiently solves race condition issues without the need to modify the cell library. Use the dynamic glitch detector to detect simulation glitches and find hard-to-find X flaws (0 / X / 1)
Detected test bench compulsion and connection problems in GLS Force / Release Propagation analysis optimizes Force and confirms undriven location of fanout logic Undriven input of X source created by verifying connectivity Supports simulations that are aware of low power consumption
Shortening turnaround time with ECO flow
Revalidate fixes from last SimXACT run after small netlist changes Use Plug and Play settings
Supports Cadence Xcelium / IES, VCS, and Questa
Effectively detect the root cause of the actual X source using the X Trace Viewer Detect the root cause of the original X that causes non-deterministic operation at reset or in normal operation mode One-step automatic Supports sequential backtrace
(Hierarchical, mixed gate level, RTL, and behavioral design)
View full X propagation time across multiple clock cycles Integrated with Verdi, SimVision, and Questa
Automatically range X in source code and waveform view to get full X propagation reference Supports interactive, command line, and batch modes With structured RTL and enhanced formal X gate level backtrace Support for the original "Controlling" feature only
Organize X Provides a report of anomalous FF to identify candidates for X that need validation
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