SimAccel

Avery
  • RTL simulation accelerator target >100-1000X speedups over simulation

  • Seamless support of simulation and accelerated VIPs

  • Full line of Accelerated VIPs (AVIP) built using high quality, proven, commercial-grade design IPs including PCIe, NVMe, AMBA AXI4/AHB/APB, DDR4, ONFI Flash

  • Integrated HW-SW co-verification using AMBA VIP/AVIP virtual prototype(VP) adapter supporting ARM, RISC-V, and MIPs VIPs including ARM Fast Models and Imperas OVPs

  • Unified HW-SW co-debug using SW/HW breakpointing and data structure inspection

  • Multi-FPGA design partitioner targets multi-FPGA board solutions up to 16 FPGAs

  • Enhanced FPGA debug visibility via Monitor AVIP supports protocol-aware debug, tracker logs, and waveforms

  • Assertion-based verification via optimized replay of accelerator trace on RTL assertions

  • Utilizes commercial and customer FPGA prototype boards, Xilinx FPGA and tools, and other 3rd party FPGA debug tools

  • Low cost alternative by fully leveraging same investment in FPGA prototype systems, design process and tools, and engineering resources

  • Comprehensive verification services to partition DUT into multiple FPGAs, integrate with ASIP/AVIP/VP IPs, implement FPGA, and run verification on DUT 

Co-simulation